| 摘要 |
By a shift register, nxd bits of data input Din are converted into parallel signals and latched by a register. A shift register is loaded with the parallel signals latched to the register when a data load signal is at high level and converts the loaded parallel signals into serial signals and outputs the serial signals as output data Dout when the data load signal is at low level. Therefore, connection between the register and the shift register is set such that a time-sequential order of the input data Din can be switched and accordingly, block interleaving can be carried out without using storages.
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