| 摘要 |
PROBLEM TO BE SOLVED: To facilitate adjustments of timings or optimizations of a layout design. SOLUTION: A replacement cell CELL1 is composed of a clock buffer CB1 and a flip-flop FF1 which latches data at a timing of falling edge of a clock signal. The final stage clock buffer positioned adjacent to a scan circuit and between the scan circuit and clock buffers which are cascaded to make up a clock tree, is replaced with the replacement cell CELL1, thereby facilitating the adjustments of the timings or the optimizations of the layout design. COPYRIGHT: (C)2007,JPO&INPIT
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