发明名称 MASTER SLAVE TYPE FLIP FLOP CIRCUIT
摘要 <p>PURPOSE:To reduce the power consumption by adding a level shift element to the high potential side of a current switching part of a master FF circuit and omitting the source follower circuit of the master FF circuit. CONSTITUTION:The drain of an FET 100 whose gate and drain are short- circuited is connected to a power line of the high potential VDD side as the level shift element, and the source is connected to load elements 91 and 92. Then, the output level of a master FF circuit 9 is reduced, and the output amplitude of a slave FF circuit 2 is sufficiently increased, and an operation margin of the circuit is obtained. Consequently, the source follower circuit of the circuit 9 is omitted to reduce the power consumption.</p>
申请公布号 JPH02292910(A) 申请公布日期 1990.12.04
申请号 JP19890113350 申请日期 1989.05.02
申请人 SUMITOMO ELECTRIC IND LTD 发明人 HIRAKATA NOBUYUKI
分类号 H03K3/3562;H03K3/356 主分类号 H03K3/3562
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