| 摘要 |
Power factor measuring apparatus receives voltage and current input signals representative of the voltage on and the current in a power line and derives rectangular voltage and current pulses from half cycles of one polarity of the input signals. The timing cycle of an adjustable timer is initiated by the crossing of the zero axis by one of the input signals, and a clocked flip-flop receiving the timer output on its clock input and the rectangular pulse derived from the other input signal on a set input changes states to provide logic 1 on its Q output when the rectangular pulse is present when the timer output is received, thereby indicating that the phase difference between voltage and current input signals is greater than the power factor bandwidth established by adjustment of the timer delay interval.
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