| 摘要 |
PURPOSE:To make the titled PLL circuit stable with less steady-state phase error by providing two systems (inverting/noninverting) output circuits for a phase comparator, connecting time to a voltage controlled oscillator through a loop filter respectively so as to cancel a DC offset voltage. CONSTITUTION:An input data (a) is subjected to strobe at the leading edge of a VCO output (b) and the output of a D flip-flop D-FF12 is as shown in figure (c). Further, the output of a D-FF23 shows a waveform delayed by 1/2 clock because the VCO output is changed by using a clock (d) inverted by an inverter 4. The output (c) of the D-FF12 and the input data (a) are given to an EOR1 circuit 5 and the output (c) of the D-FF12 and the output (e) of the D-FF23 are given to an EOR2 circuit 6 to obtain output signals of the EOR circuits 5, 6. The output signal (f) of an EOR1 circuit 5 represents a phase error signal and becomes an inverting input to a differential amplifier 7 and the output signal (g) of the EOR2 circuit 6 is given to the noninverting input of the differential amplifier 7 as a reference signal and the noninverting output (h) and the inverting output (i) of the differential amplifier 7 become control signals to the PLL circuit. In the case of the state (1), the DC level of the con trol signals (h, i) is 0 to show that the PLL circuit is in a stable point. |
