| 摘要 |
PROBLEM TO BE SOLVED: To perform verification of reflecting wiring RC information on circuit simulation from the early stage of layout design by easily coupling a circuit net list generated from circuit data and a wiring RC net list extracted from layout data. SOLUTION: A circuit information fetching processing means 6 fetches circuit information for circuit data 2 at the initial stage of layout design. A layout designing means 7 designs the layout data while using the same name as the instance name and net name of a function block in the circuit data for a cell arranged on the top hierarchy and a net connected between cells. By allocating port information composed of the instance name and the net name to the circuit data 2 and layout data 8, the same name node is outputted to a circuit net list 5 and a wiring RC net list 11, thus easily merging the wiring RC net list 11 to the circuit net list 5 and an inter-cell net.
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