发明名称 METHOD AND DEVICE FOR VERIFYING LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To exactly detect a spot, where a through current is generated by an HiZ entry, in a logic simulation. SOLUTION: This device is provided with a floating deciding part 3 for detecting a spot, where the through current is generated by gate floating of an MOS transistor caused by an HiZ value entry making the output of a verification target cell into unfixed value, on the basis of a decision function F34 prepared from the circuit chart of a real device, which does not depend on the description of a library F3 for logic simulation in a verification target circuit.
申请公布号 JP2002163322(A) 申请公布日期 2002.06.07
申请号 JP20000363053 申请日期 2000.11.29
申请人 NEC MICROSYSTEMS LTD 发明人 EZAKI KUMIKO
分类号 G01R31/28;G06F17/50;(IPC1-7):G06F17/50 主分类号 G01R31/28
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