| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a faster transistor logic circuit. <P>SOLUTION: An input inverter section 10 inverts a plurality of input signals a, b, c, to produce complementary signals inverse of a, inverse of b, inverse of c and gives the input signals and the complementary signals to a logic circuit network 20. The logic circuit network 20 comprises a plurality of pairs of depletion NMOSes (NDMOSes) whose conductive state is complementarily controlled by a given signal. Since a threshold voltage set negative is given to the NDMOSes, the NDMOSes are not completely turned off because of flowing of a drain current even when a gate voltage is 0V. Thus, the change from the OFF state to the ON state is quickly carried out and a signal at the "H" level of a node M to which the signal of a logic arithmetic result is outputted is raised to the same potential as a power supply potential VDD. The signal at the node M is outputted from an output buffer section 30 as an output signal OUT. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
