发明名称 |
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region |
摘要 |
A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions separated by a central inactive region. The cell layout also includes a gate electrode level layout for the entire cell defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal and minimized across the gate electrode level layout. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.
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申请公布号 |
US2010023908(A1) |
申请公布日期 |
2010.01.28 |
申请号 |
US20090572212 |
申请日期 |
2009.10.01 |
申请人 |
TELA INNOVATIONS, INC. |
发明人 |
BECKER SCOTT T.;SMAYLING MICHAEL C. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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地址 |
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