Channel estimation in wireless communication

摘要

A channel estimation processor for a receiver in a wireless communication system is described. The channel estimation processor includes a stage-1 processor (STG1) arranged to pluralities of Nsym reference symbol correlation values per slot. The channel estimation processor includes a stage-2 processor (STG2) comprising a plurality of stage-2a processors for obtaining filtered outputs per slot, a respective plurality of stage-2b processors for obtaining respective slot filter results and a stage-2 adder (STG2ADD) for obtaining channel estimates for respective anchor positions. The stage-2a processors are arranged to filter respective pluralities of reference symbol correlation values using respective reference symbol filters (ga) to obtain a respective filtered output per slot. The stage-2b processors (STG2B1) are arranged to filter a predetermined number of Nslots associated filtered reference outputs using respective slot filters (a) with respective slot-specific filter coefficients (ai) to obtain a first slot filter result. The stage-2 adder (STG2ADD) is arranged to sum the slot filter results to obtain the channel estimate for anchor symbol positions. An interpolator is arranged to, for symbol positions different from anchor symbol positions, determine a channel estimate for the symbol position from interpolating the channel estimates for two closest anchor symbol positions.