发明名称 Integrierte Schaltungsanordnung mit komplementaeren Transistoren
摘要 1,204,526. Semi-conductor device. THOMSON-CSF. 17 Oct., 1967 [28 Oct., 1966], No. 47324/67. Heading H1K. An integrated circuit comprises complementary NPN and PNP transistors, N<SP>1</SP> 1 +P 1 N 1 and P 2 N 2 (P<SP>111</SP>+P<SP>1</SP>) respectively, on a P-type substrate (P<SP>1</SP>P + ) which serves as the collector for the PNP transistor. The N-type base N 2 of this PNP transistor is deposited on the substrate, and its P-type emitter P 2 is deposited upon this N-type base. A further N-type layer N<SP>1</SP> 2 + is deposited on this emitter to form an NPN further transistor N 2 P 2 N<SP>1</SP> 2 + combined with the PNP transistor and having a low emitter-base junction impedance connecting the PNP transistor base N 2 to the ohmic contact E<SP>1</SP> 2 . Walls P<SP>11</SP>+ isolate the transistors from one another.
申请公布号 DE1589643(A1) 申请公布日期 1970.04.30
申请号 DE19671589643 申请日期 1967.10.27
申请人 CSF-COMPAGNIE GENERALE DE TELEGRAPHIE SANS FIL 发明人 BLANLUET,JACK;PIERRE POLLARD,JEAN;ROUX,GERARD LE
分类号 H01L21/74;H01L27/082 主分类号 H01L21/74
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