| 摘要 |
1279816 Transistor bi-stable circuits INTERNATIONAL BUSINESS MACHINES CORP 14 Nov 1969 [23 Dec 1968] 55771/69 Heading H3T [Also in Division H1] The bi-stable memory unit of Fig. 1 is made in the integrated form shown in Fig. 3 in which the two double emitter NPN transistors are formed in a single junction-isolated pocket. (The incidental resistance 60 is made as high as possible by providing a suitably large spacing between the two transistors.) The structure is formed on a P<SP>+</SP> substrate upon which an N-type epitaxial deposition is made in two stages, the N<SP>+</SP> subcollectors being formed by diffusion between the two stages. The remainder of the processing-the formation of emitters, bases, connections 38 to the subcollectors and formation of the isolation walls 18-involves normal diffusion and is followed by suitable metallization. The non-linear diodes D 1 and D 2 are distributed diodes formed by the substrate to epitaxial layer junction, the power supply being connected to the substrate. To ensure bi-stable operation, the dynamic impedance of the diodes is made greater than that of the emitter-base diodes by making the doping levels n conform to the relationship (n 16 /n 14 )>(n 26 /n 22 ). |
