| 摘要 |
In a digital audio or digital video recording channel, a pseudo clock extractor receives a reference clock (212, 306) having a periodicity n times (n >/= 4) or preferably 2<n> times (n >/= 2) the frequency of an audio data clock signal, the reference clock triggering in and synchronizing to a biphase-mark encoded data stream (222, 302). Data transitions in the data stream are detected and each transition resets a modulo-counter (240) to a pre-specified value so that in combination with the reference signal, the audio data clock signal (242, 326) is synchronous to the triggered-in data stream, the audio data clock rising transition edges being near half-bit cell centers of the triggered-in data stream. |
