发明名称 ERROR PROCESSING SYSTEM
摘要 PURPOSE:To process effectively an error which is due to a soft error, by holding the error information on the area where the error arises, controlling the writing and reading and transmitting the error information to a fault processor when a correctable error of the reading data is detected by a dRAM of an MOS. CONSTITUTION:This error processing system includes a CPU400, a main memory 500, an address circuit 100, a data circuit 200 and a control circuit 300. The memory 500 consists of a dRAM of an MOS. When a correctable error of the reading data is detected, the error information that specifies the area of the fault is held. In case a correctable error is detected for the reading data following the reading data from which no error is detected, the writing and reading is performed on the basis of the held error information. As a result, a correctable error due to a soft error is distinguished from a fixed error. Thus a quick correction is given to the faulty area.
申请公布号 JPS5885999(A) 申请公布日期 1983.05.23
申请号 JP19810183304 申请日期 1981.11.16
申请人 NIPPON DENKI KK 发明人 YOSHIDA NAOTERU
分类号 G11C29/00;G06F11/07;G11C29/42 主分类号 G11C29/00
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