发明名称 |
PHASE-LOCKED LOOP SYSTEM WITH A PHASE-ERROR SPREADING CIRCUIT |
摘要 |
A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.
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申请公布号 |
US2010020910(A1) |
申请公布日期 |
2010.01.28 |
申请号 |
US20080180166 |
申请日期 |
2008.07.25 |
申请人 |
BHAGAVATHEESWARAN GAYATHRI A;CAO LIPENG;SANCHEZ HECTOR |
发明人 |
BHAGAVATHEESWARAN GAYATHRI A.;CAO LIPENG;SANCHEZ HECTOR |
分类号 |
H03D3/24 |
主分类号 |
H03D3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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