发明名称 Memory device
摘要 A memory device which includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data, and a controller having a first data input connected to receive first data, a second data input connected to receive second data, a third data input connected to receive a function mode signal, and operation unit for executing operations between the first data and the second data. The operation unit includes a function setting unit for setting a function indicated by a function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the set function is executed for the first and second data. The operation result is written into the selected part of the storage locations during one memory cycle.
申请公布号 US2002093852(A1) 申请公布日期 2002.07.18
申请号 US20020059328 申请日期 2002.01.31
申请人 KIMURA KOICHI;OGURA TOSHIHIKO;AOTSU HIROAKI;IKEGAMI MITSURU;KUWABARA TADASHI;ENOMOTO HIROMICHI;KYODA TADASHI 发明人 KIMURA KOICHI;OGURA TOSHIHIKO;AOTSU HIROAKI;IKEGAMI MITSURU;KUWABARA TADASHI;ENOMOTO HIROMICHI;KYODA TADASHI
分类号 G11C5/06;G11C7/00;G11C13/00;(IPC1-7):G11C5/06 主分类号 G11C5/06
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