| 摘要 |
PURPOSE:To reduce the input capacitance of the J-FET, and to increase mutual conductance by lowering the impurity concentration of an epitaxial layer and augmenting the impurity concentration of a channel section. CONSTITUTION:The epitaxial layer having 10<14>atom/cm<3> impurity concentration is grown to a P<+> type semiconductor substrate 1 having 10<19>atom/cm<3> impurity concentration. A P type impurity is thermally diffused, the island 7 of an N type epitaxial layer is formed, and N<+> type regions 3 having 10<21>atom/cm<3> impurity concentration functioning as a source and a drain are shaped. A photo-resist 8 is applied, photo-resist sections 8 corresponding to a region serving as one part of a gate and one parts of the N<+> type regions 3 are removed, and an N type region having 10<15>-10<16>atom/cm<3> impurity concentration is formed to the channel section 9 from the sections removed. The P<+> region 4 functioning as one part of the gate is shaped, a silicon dioxide film 5 is bored, and a metal is wired. |
