CIRCUIT FOR GENERATING SIGNAL FOR CONTROLLING DATA SWITCH FOR READ OPERATION OF DDR SDRAM

摘要

PURPOSE: A circuit for generating signal for controlling data switch for read operation of DDR SDRAM is provided to generate a QFCB signal for the read operation of a DDR SDRAM operating fast and exactly although an interrupt or a read order is continuously inputted CONSTITUTION: The device includes an output driving signal generating circuit and an output buffering circuit. The output driving signal generating circuit outputs an inputted data strobe enable signal when a reading order is applied to first and second control signals and the second control signal become 'enable'. The first control signal forms a data window as a bust length at the writing operation to make an 'enable' a data switch controlling signal. The second control signal decides whether the data switch controlling signal is used or not when an extension mode register set order is performed. The output buffering circuit maintains a high impedance level and performs a pull down operation only when an output of the output driving signal generating circuit becomes enable