| 摘要 |
1,147,553. Radio navigation. INTERNATIONAL STANDARD ELECTRIC CORP. 22 March, 1967 [31 March, 1966], No. 13457/67. Addition to 1,147,552. Heading H4D. The Specification describes a digital TACAN receiver, using the modulation crossover selector described in Specification and a basic counter system as described in the parent Specification 1,147,552. Thus the coarse 15 cycles/sec. modulation envelope is detected to produce a pulse train B, Fig. 2, defining the positive crossover points and a pulse train C defining the negative crossover points. The 15 cycle/sec. north reference pulses A are also detected. The fine 135 cycles/sec. modulation envelope is also detected to produce pulse trains indicating positive and negative crossover points. The 15 cycles/sec. crossover pulse trains B and C are fed to inputs 12 and 13, Fig. 1, of 15-cycle modulation crossover selector 18 and the 15- cycle north reference pulses A are fed to selector 18, to reset input of bi-stable circuit 16 and to a counter 17 which is sequentially switched through stages 1 to 8 (E, Fig. 2) by successive reference pulses. The 135 cycles/sec. crossover pulse trains are similarly fed to 135 cycle modulation crossover selector 29 and the 135-cycle north reference pulses fed to selector 29, to the set input of bi-stable circuit 27 and to counter 28 which is thereby sequentially switched through stages 1 to 8. The selectors 18 and 29, select that crossover pulse train which is furthest away from the respective north reference pulse train. A signal is fed to AND gate 21 if the positive crossover pulse train is selected, and to AND gate 21 if the negative crossover pulse train is selected. In the present case, the positive crossover pulse train is selected (D) and appears at the output of the selector for application to the set input of circuit 16. In the 1 state, counter 17 produces a signal enabling AND gate 20 which in turn produces a signal which presets a binary digital counter A, 19, to 380‹ (Waveform F, Fig. 2). (If the negative crossover pulse train had been selected, AND gate 21 would have preset the counter to 200‹.) The counter is set to 20‹ above 360‹ or 180‹, to allow for up to 20‹ phase jitter. The first selected crossover pulse D sets circuit 16, and the following north reference pulse resets the circuit. Circuit 16 thus produces a gate having a width proportional to the coarse bearing, and this is applied via OR circuit 23 to open gate 24 so as to pass clock pulses of frequency F, from generator 25 to counter 19. These pulses cause counter 19 to count down, such that a count of 300‹ is passed through, and a signal appears at output 22, indicating to the selector 18 that the choice of the positive crossover pulse train was correct. A signal will appear at output 41, indicating a reached count of 200‹, if the choice is incorrect. Once the choice is verified, the count returns to 380‹ at the beginning of the state 2. During states 2 through 5, circuit 16 produces gates of said width whereby counter 19 counts down, until at the end of state 5, the count in counter 19 is equal to the coarse bearing plus 20‹. Also during state 5 counter 28 is actuated and counts through 8 sub-states. Assuming the positive 135-cycle crossover pulse train to have been selected by selector 29, AND gate 30, causes 0 to 40‹ counter 32 to be preset to 0‹ (as against 20‹ for the negative crossover pulse train), (waveform G, Fig. 2). The bi-stable circuit 27 produces a gate pulse for each of the sub-states, such that after a crossover pulse train choice verification, the count in counter 32 increases due to pulses from generator 25 up to a count representing the fine component of the true bearing (e.g. if the true bearing is 256‹, the count is 16‹). Thus, using the assumed above true bearing, at the end of state 5 counter 32 holds a count of 16‹ and counter 19 holds a count of 286‹, i.e. 256‹ plus the added 20‹, plus an error of 10‹. The fine (up to 40‹) component of the coarse bearing is held in the early bits of counter 19 up to that bit having a significance of 20‹. The contents of these early bits are thus compared with the count in counter 32 by means of comparator 37. In state 6 a gate from circuit 38 opens gate 24 to the output of generator 25, such that the count in counter 19 decreases until the two compared counts are equal and comparator 37 produces a signal ending the gate from circuit 38. The count in counter 19 is now equal to the true bearing 256‹. At the beginning of state 7, the count in counter 32 is returned to 0‹ and the faster output of generator 36 is then fed to counter 32 such that its capacity (weighting) changes from 40‹ to 360‹. The count in counter 19 decreases to 0‹, whence an output from the counter opens gates 39 receiving the parallel contents of the bits of counter 32. The thus gated contents represent the required true bearing 256‹. After reaching 0‹ counter 19 returns to 380‹ and continues its decreasing count. Thus at the end of state 7 the count is equal to the count at the end of state 5, thus bypassing states 1 to 4. |
