| 摘要 |
PURPOSE:To provide the digital signal processing circuit in which number of channels for convolution calculation or summing form of channel outputs are selected depending on application. CONSTITUTION:Selectors SLI-SL7 are provided among convolution devices BK0-BK7, and when a channel mode is designated to '4' and a summing mode is designated to be '2', the circuit is connected as shown in broken lines in figure. Thus, a digital signal string is fed to a data memory 1 of even number convolution devices BK0, BK2,... and the digital signal from the convolution devices is fed to odd number convolution devices BK1, BK3,... in the order of older signals. Furthermore, selectors SL8-SL14 (not shown) are provided among the convolution devices and the convolution results of the convolution devices BK0-BK3, BK4-BK7 are added and the result is controlled to be outputted. |
