| 摘要 |
1,207,350. Digital computers. GENERAL ELECTRIC CO. 13 Dec., 1967 [13 Dec., 1966], No. 56731/67. Heading G4A. In an information processor, terminal states of two shift registers are gated to respective inputs of a full adder under control of first and second values of a terminal state of a third shift register respectively, the three registers being shifted in synchronism, and the adder output being shifted into one of the first two registers. The operand address portion of a " field " command (instruction) in the I register accesses an operand word from memory into the B register. The command is decoded to produce one of the signals DLDF, DSTF, DAFA, DSFA, DTFL, DTFE to cause one of the following operations respectively, the A, B and Q registers in each case being shifted out simultaneously via the low-order ends by shift pulses FSRF until a clock-driven counter reaches a predetermined count (equal to register capacity). Load field.-Each bit of the A register which corresponds to a 1 in the Q register is replaced by the corresponding bit of the B register as follows: Each bit of the Q register, according to its value, gates the corresponding bit from either the A register or the B register into the F serial full adder (which does not modify it) as the registers are shifted out, the adder " sum' output being shifted into the A register. Store field.-Each bit of the B register which corresponds to a 1 in the Q register is replaced by the corresponding bit of the A register, in a similar way to " load field." The contents of the B register are then transferred in parallel into the memory location from which the B register was orignally loaded. Add field to A.-Those bits of the B register corresponding to 1 in the Q register are added in the F serial full adder to the corresponding bits from the A register, the result (including the unmodified A register bits) being shifted into the A register. Carry into a bit position corresponding to a 0 in the Q register is prevented at NAND gate G518, and AND gate G544 clears the carry flip-flop 27A when a 0 arrives from the Q register in preparation for the next 1 from the Q register. Subtract field from A.-This is similar to " add field to A " except that the contents of each field of the B register (a " field " being a series of consecutive bits corresponding to 1's in the Q register) are supplied to the F full adder in two's-complement form. This is achieved by taking the inverse of each bit at AND gate G543 and adding 1 into each field by presetting the carry flip-flop 27A from AND gate G546 for each field. Test field less.-The contents of the B register are subtracted from the contents of the A register in the F full adder as in " subtract field from A," a test flip-flop 69 (initially cleared) being set via AND gate G551 if a carry from the F full adder is absent at any time the Q register is supplying a 1. Thus the test flip-flop will be set if A is less than B in any field corresponding to 1's in the Q register. Test field equal.-This is like " test field less " except that the test flip-flop (initially set) is cleared via AND gate G555 if a sum bit of 1 occurs from the F full adder at the same time the Q register is supplying 1 since this indicates inequality. During the " store field," " test field less " and " test field equal " commands, the contents of the A register are recirculated without change via the N full adder shown. In all field commands the contents of the Q register are recirculated without change. The features of the computer of Specification 1,207,167 (circular lists mainly) may be incorporated, it is stated. |
