TIMING SYSTEM REDUCED IN SKEWNESS FOR WRITE-IN CIRCUIT USED FOR MEMORY CIRCUIT

摘要

PROBLEM TO BE SOLVED: To reduce timing skewness at writing in a memory circuit. SOLUTION: In the write-in timing system reduced in skewness, a signal on a write-in data line for a memory circuit and a signal on a write-in column selecting line are clocked at an edge which is opposite to a clock signal. Consequently, sensitivity with respect to timing at write-in is relaxed. It is preferable that duty cycle of a clock be approximately 50%, and further it is most preferable that duty cycle be within 5% of that.