发明名称 Selecting die placement on a semiconductor wafer to reduce test time
摘要 A die placement of dies on a wafer is selected to reduce test time of the dies by obtaining a die placement and determining placements of a tester head needed to test the dies in the die placement. A number of touchdowns needed in the determined placements of the tester head is determined, where a touchdown involves lowering the tester head to form an electrical contact between pins on the tester head and bonding pads on a die being tested. The die placement is adjusted to reduce the number of touchdowns.
申请公布号 US7190183(B1) 申请公布日期 2007.03.13
申请号 US20040799061 申请日期 2004.03.12
申请人 PDF SOLUTIONS, INC. 发明人 CADOURI EITAN
分类号 G01R31/02 主分类号 G01R31/02
代理机构 代理人
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