发明名称 |
Semiconductor integrated circuit device with test circuit |
摘要 |
A semiconductor integrated circuit device includes a memory circuit and a flag generator. The memory circuit is a circuit with a test circuit and includes a redundant circuit. The flag generator loads compared result information serially output from the memory circuit, and outputs flag signals if the compared result information includes at least one piece of mismatch information. This makes it possible to solve a problem of a conventional semiconductor integrated circuit device in that it takes a long time for carrying out a fault test of bits constituting the memory circuit.
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申请公布号 |
US6397363(B1) |
申请公布日期 |
2002.05.28 |
申请号 |
US19990435622 |
申请日期 |
1999.11.08 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MAENO HIDESHI;OSAWA TOKUYA |
分类号 |
G01R31/28;G06F11/00;G06F11/22;G06F12/16;G11C29/00;G11C29/12;G11C29/40;G11C29/44;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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