Circuits for Locally Generating Non-Integral Divided Clocks with Centralized State Machines

摘要

Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal. A local pass gate receives the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal.