FSK decoding using envelope comparison in the digital domain

摘要

A method of FSK decoding includes generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk). From R'Edge and Sys_clk clocks are generated including a first clock and second clock framing a logic ‘0’ level of the FSK signal, and a third clock and fourth clock framing a logic ‘1’ level of the FSK signal. At least four frequency envelopes are generated from the clocks including a logic ‘0’ envelope, a logic ‘1’ envelope, a lower frequency envelope below the logic ‘0’ envelope, and an upper frequency envelope above the logic ‘1’ envelope. R'Edge is compared to the four envelopes, and a decoded output is produced, logic ‘0’ if the R'Edge overlaps the logic ‘0’ envelope, logic ‘1’ if R'Edge overlaps the logic ‘1’ envelope, and a previous output state if R'Edge does not overlap the logic ‘0’ or logic ‘1’ envelope.

主权项

1. A method of frequency-shift keying (FSK) decoding, comprising:
generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk); generating a plurality of clocks from said R'Edge and said Sys_clk including a first clock and second clock framing a frequency for a logic ‘0’ level of said FSK signal, and a third clock and fourth clock framing a frequency for a logic ‘1’ level of said FSK signal; generating at least four frequency envelopes from said plurality of clocks including a logic ‘0’ envelope, a logic ‘1’ envelope, a lower frequency envelope below said logic ‘0’ envelope, and an upper frequency envelope above said logic ‘1’ envelope; comparing said R'Edge to said four frequency envelopes, and outputting a decoded output of said logic ‘0’ if said R'Edge overlaps said logic ‘0’ envelope, said logic ‘1’ if said R'Edge overlaps said logic ‘1’ envelope, and a previous output state if said R'Edge does not overlap said logic ‘0’ envelope or overlap said logic ‘1’ envelope.