| 发明名称 | High speed latch and method | ||
| 摘要 | An embodiment latch device includes a first stage having circuitry that receives a differential input and generates a clocked data signal according to a clock signal and the differential input, and a second stage connected to the first stage and having circuitry that generates differential outputs according to the clock signal and the clocked data signal. The second stage further has a reset circuit that resets a latch storage to a high value according to the clock signal. | ||
| 申请公布号 | US9438211(B1) | 申请公布日期 | 2016.09.06 |
| 申请号 | US201514801473 | 申请日期 | 2015.07.16 |
| 申请人 | HUAWEI TECHNOLOGIES CO., LTD. | 发明人 | Chong Euhan |
| 分类号 | G11C7/00;H03F3/45;H03K3/356;H03K3/012 | 主分类号 | G11C7/00 |
| 代理机构 | Slater Matsil, LLP | 代理人 | Slater Matsil, LLP |
| 主权项 | 1. A latch device comprising: a first stage having circuitry that receives a differential input and generates a clocked data signal according to a clock signal and the differential input; and a second stage connected to the first stage and having circuitry that generates differential outputs according to the clock signal and the clocked data signal, the second stage further having a reset circuit that resets a latch storage to a high value according to the clock signal, wherein the clock signal causes the reset circuit to reset the latch storage and causes the first stage to reset in a same portion of a cycle of the clock signal. | ||
| 地址 | Shenzhen CN | ||