发明名称 VARIABLE LENGTH DECODER
摘要 <p>PURPOSE:To provide the variable length decoder in which the capacity of a lookup table is made small so as to reduce the hardware scale. CONSTITUTION:A prefix data generating section 17 compares plural bits from a head of a bit string having a prescribed bit number outputted from a barrel shifter 11 with a prescribed pattern and generates a bank address of a small bit number allocated to the prescribed pattern when the both are coincident. The lookup table 14 uses the bank address as a high-order address and uses plural remaining bits resulting from eliminating a prescribed pattern coincident among code bits for a low-order address so as to apply addressing to decoded data.</p>
申请公布号 JPH07235878(A) 申请公布日期 1995.09.05
申请号 JP19940266475 申请日期 1994.10.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MIYAKOSHI EIJI;IMANISHI HIROSHI;TAKENO KOJI
分类号 G06F5/00;H03M7/42;H04B14/06;H04N1/41;H04N7/24;H04N19/132;H04N19/134;H04N19/136;H04N19/18;H04N19/189;H04N19/196;H04N19/423;H04N19/426;H04N19/436;H04N19/51;H04N19/625;H04N19/85;H04N19/91;(IPC1-7):H03M7/42 主分类号 G06F5/00
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