发明名称 PATTERN VERIFYING METHOD AND VERIFYING DEVICE
摘要 <p>PURPOSE:To speed up pattern verification by separating a pseudo defect from an intrinsic defect, detecting this pseudo defect in this state and not picking up this detected pseudo defect as the intrinsic defect pattern. CONSTITUTION:This pattern verifying device has a first graphic processing data memory section 8 for registering the patterns after logic processing by a logic processing means 7 as pattern graphics. A pseudo defect pattern detecting means 10 for detecting the pattern with which the size of the pattern graphics attains the value below the predetermined value in accordance with the coordinates of the pattern graphics registered in this first graphic processing data memory section 8 is included in a data processing section 2. The pattern detected by this pseudo defect pattern detecting means 10 is judged as the pseudo defect pattern, i.e., non-defect pattern and is discriminated from the defect pattern to be intrinsically detected, thereby, the pattern verification is executed. The detection of the intrinsic defect in the pattern after sizing processing is executed by a defect pattern detecting means 11.</p>
申请公布号 JPH07261372(A) 申请公布日期 1995.10.13
申请号 JP19940048939 申请日期 1994.03.18
申请人 FUJITSU LTD 发明人 HAGINO ICHIRO;TAWARA KATSUJI
分类号 G01B11/24;G03F1/08;G06T7/00;H01L21/027;H01L21/66;(IPC1-7):G03F1/08 主分类号 G01B11/24
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