| 摘要 |
<p>A synchronization system aligns video signals without the use of phase locked loop. One embodiment includes a delay line (220) and a selection circuit (250). A clock signal (CLKIN) with a desired frequency for a pixel clock is applied to the delay line (220) to generate a series of delayed signals at taps on the delay line. When a transition in a horizontal sync signal occurs, the selection circuit (250) senses delayed signals and selects a delayed signal having a transition aligned relative to the transition in the horizontal sync signal. This delayed signal is a pixel clock signal which is not subject to frequency fluctuation of a phase locked loop. Selecting a new delayed signal at each horizontal blanking period keeps the pixel clock for each line of video aligned to the horizontal sync signal.</p> |
