发明名称 |
Method and apparatus for efficient utilization for prescient instruction prefetch |
摘要 |
Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread. |
申请公布号 |
US7404067(B2) |
申请公布日期 |
2008.07.22 |
申请号 |
US20030658072 |
申请日期 |
2003.09.08 |
申请人 |
INTEL CORPORATION |
发明人 |
AAMODT TOR M.;WANG HONG;HAMMARLUND PER;SHEN JOHN P.;LIAO STEVE SHIH-WEI;WANG PERRY H. |
分类号 |
G06F9/38;G06F9/30;G06F9/46 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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