Semiconductor device provided with an IE type trench IGBT

摘要

A switching loss is prevented from being deteriorated by suppressing increase in a gate capacitance due to a cell shrink of an IE type trench gate IGBT. A cell formation region is configured of a linear active cell region, a linear hole collector cell region, and a linear inactive cell region between them. Then, upper surfaces of the third and fourth linear trench gate electrodes which are formed so as to sandwich both sides of the linear hole collector cell region and electrically connected to an emitter electrode are positioned to be lower than upper surfaces of the first and second linear trench gate electrodes which are formed so as to sandwich both sides of the linear active cell region and electrically connected to a gate electrode.

主权项

1. A semiconductor device provided with an IE type trench IGBT comprising:
(a) a semiconductor substrate which has a first main surface and a second main surface opposite to the first main surface; (b) a collector region which is formed in the semiconductor substrate and which has a first conductivity type; (c) a drift region which is formed in the semiconductor substrate on the collector region and which has a second conductivity type different from the first conductivity type; (d) a plurality of linear unit cell regions which are formed along a first direction in the semiconductor substrate on the drift region and each of which is formed of a first linear unit cell region and a second linear unit cell region; (e) a gate electrode provided on the first main surface side; (f) an emitter electrode provided on the first main surface side; and (g) a collector electrode provided on the second main surface side, the first linear unit cell region including: (x1) a linear active cell region provided from the first main surface to inside; (x2) a first trench and a second trench which are formed so as to sandwich both sides of the linear active cell region in the first direction and so as to have a first depth from the first main surface; (x3) a first linear trench gate electrode and a second linear trench gate electrode which are electrically connected to the gate electrode and which are formed inside the first trench and the second trench, respectively; (x4) an emitter region of the second conductivity type which is formed in the linear active cell region so as to have a second depth from the first main surface; (x5) a first body region of the first conductivity type which is formed below the emitter region of the linear active cell region so as to have a third depth deeper than the second depth from the first main surface; (x6) a first linear inactive cell region provided on both sides of the linear active cell region in the first direction via the first trench and the second trench; and (x7) a first floating region of the first conductivity type which is formed in the first linear inactive cell region so as to have a fourth depth from the first main surface, and the second linear unit cell region including: (y1) a linear hole collector cell region provided from the first main surface to inside; (y2) a third trench and a fourth trench which are formed so as to sandwich both sides of the linear hole collector cell region in the first direction and so as to have the first depth from the first main surface; (y3) a third linear trench gate electrode and a fourth linear trench gate electrode which are electrically connected to the emitter electrode and which are formed inside the third trench and the fourth trench, respectively; (y4) a second body region of the first conductivity type which is formed in the linear hole collector cell region so as to have the third depth from the first main surface; (y5) a second linear inactive cell region provided on both sides of the linear hole collector cell region in the first direction via the third trench and the fourth trench; and (y6) a second floating region of the first conductivity type which is formed in the second linear inactive cell region so as to have the fourth depth from the first main surface, wherein, further, upper surfaces of the third linear trench gate electrode and the fourth linear trench gate electrode are positioned to be lower than upper surfaces of the first linear trench gate electrode and the second linear trench gate electrode.