发明名称 Rewriting symbol address initialization sequences
摘要 A system includes a memory to store a linker and one or modules, and a processor, communicatively coupled to the memory. The computer system is configured to recognize a first symbol address initialization sequence in a module. The system determines whether the first symbol address initialization sequence is a candidate for replacement, determines whether to replace the first symbol address initialization sequence with a second symbol address initialization sequence, and replaces the first symbol address initialization sequence with the second symbol address instruction sequence when it is determined to replace the first symbol address initialization sequence with the second symbol address initialization sequence.
申请公布号 US9384130(B2) 申请公布日期 2016.07.05
申请号 US201414570000 申请日期 2014.12.15
申请人 International Business Machines Corporation 发明人 Gschwind Michael Karl;Weigand Ulrich
分类号 G06F9/44;G06F12/06 主分类号 G06F9/44
代理机构 代理人 Wilhelm Richard A.;Bennett Steven L.
主权项 1. A computer-implemented method for linking object code comprising: recognizing a first symbol address initialization sequence in a module by determining that first symbol address initialization sequence corresponds with a pre-defined symbol address instruction sequence, wherein the first symbol address initialization sequence includes one or more instructions for loading an address in a first register of a processor, the one or more instructions including an instruction that depends on a value stored in a second register of the processor, the first register for storing an address of a table of contents (TOC) and the second register for storing a starting address of the module; determining whether to replace the first symbol address initialization sequence with a second symbol address initialization sequence by determining whether a first condition is satisfied, wherein the first condition is that the second symbol address initialization sequence has a second processor resource usage that is less than a first processor resource usage associated with the first symbol address initialization sequence; and replacing the first symbol address initialization sequence with the second symbol address instruction sequence when it is determined that the first condition is satisfied.
地址 Armonk NY US
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