发明名称 Package and method for integration of heterogeneous integrated circuits
摘要 A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.
申请公布号 US9419156(B2) 申请公布日期 2016.08.16
申请号 US201314015513 申请日期 2013.08.30
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Lee Wan-Yu;Tseng Chun-Hao;Lai Jui Hsieh;Huang Tien-Yu;Kuo Ying-Hao;Yee Kuo-Chung
分类号 H01L31/0232;H01L23/48;H01L21/50;H01L23/31;H01L31/09;H01L23/00;H01L27/146;H01L23/538 主分类号 H01L31/0232
代理机构 Eschweiler & Associates, LLC 代理人 Eschweiler & Associates, LLC
主权项 1. A package for holding a plurality of heterogeneous integrated circuits, comprising: a first chip having a first conductive pad and a first substrate, the first substrate including a first semiconductor; a second chip having a second conductive pad and a second substrate, the second substrate including a second semiconductor, wherein the second semiconductor is different from the first semiconductor; a molding structure, the first chip and the second chip embedded in the molding structure, wherein a top surface of the molding structure, a top surface of the first chip and a top surface of the second chip are co-planar; a conductive structure over the first chip and the second chip, the conductive structure conductively coupled to the first conductive pad; and a passivation layer over the conductive structure, the passivation layer comprising an opening defined therein, the opening exposing a portion of the second chip; wherein the second conductive pad is a n-type contact, the n-type contact comprising: a first metal layer over the second substrate, a second metal layer over the first metal layer, a third metal layer over the second metal layer, and a fourth metal layer over the third metal layer.
地址 Hsin-Chu TW