| 摘要 |
PURPOSE:To simplify circuit constitution while reducing power consumption by providing two gate circuits and a reset priority FF circuit. CONSTITUTION:Gate circuit (e) and (f) and reset priority FF circuit (g) are provided. When the clock signal of terminal 2 is [0], the outputs of terminals 6 and 7 are [1] and [0], and circuits (e) and (g) are impassive and active states respectively. At this time, when the data signal of input 1 is [1], terminal 4 is [1] and when [0], terminal 4 is [0]; and since circuit (g) is impassive, terminal 3 is [0] without reference to the input data. Next, when the clock signal is [1], the opposite states to those mentioned above are set. Namely, terminal 3 is [1] only when input data is [1] and clock signal is also [1] the moment the clock signal changes from [0] to [1], so that this circuit will discriminates the input data momentarily at the point in time of the rise of the block so as to send the RZ waveform. |
