| 摘要 |
A semiconductor memory system providing memory matrix area where many word lines and bit lines cross in the row and column directions. Memory cells are arranged at the intersections resulting in high integration density. A plurality of peripheral circuit blocks connected to adjacent plurality of word lines or bit lines. For example, the sense amplifiers and decoder circuits, etc., are sequentially arranged in files against the direction of the bit lines and word lines, respectively. Thereby, connections between the word lines or bit lines and the peripheral circuit blocks can be made without complicating the structure and using chip area ineffectively.
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