发明名称 SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To stabilize the operation of an EEPROM and the like and to make the cost thereof low by enlarging operational margin of the EEPROM and the like provided with a dummy cell and shortening the time require for a retention test. CONSTITUTION:A writing circuit for a dummy cell DW is provided in the EEPROM and the like provided with the dummy cell Dc, and the substantial signal quantity for writing to the dummy cell Dc is selectively switched to intentionally switch its substantial threshold voltage switched from the outside intentionally. Thereby, when a threshold voltage of the dummy cell Dc is varied by being influenced by manufacturing process and the like, the value of the threshold voltage is switched from the outside, and corrected to a desired value. Also, at the time of the retention test, the threshold voltage of the dummy cell Dc is forcedly biased, the time required for the retention test is shortened.</p>
申请公布号 JPH07130190(A) 申请公布日期 1995.05.19
申请号 JP19930296075 申请日期 1993.11.01
申请人 HITACHI LTD;HITACHI VLSI ENG CORP 发明人 NAKAJIMA SHIGERU;SHIMOZATO TAKESHI;YASHIRO KAZUSATO;FURUNO TAKESHI
分类号 G11C17/00;G11C16/06;(IPC1-7):G11C16/06 主分类号 G11C17/00
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