发明名称 |
HIGH SPEED DIGITAL DATA RE-TIMING DEVICE |
摘要 |
<p>PROBLEM TO BE SOLVED: To apply re-timing to data stably even when a static skew due to a difference of delay between a re-timing clock pulse and data bits and a dynamic skew due to a change in time and temperature are in existence in binary data bits sent at a high speed. SOLUTION: The device is provided with a means 201 generating nsets of multiple phase clock pulses with n-phases from an external input clock pulse, a means 202 providing an output of a control signal to select one clock pulse or over whose transition takes place close to the middle of an interval of data bits received externally among the n-sets of multiple phase clock pulses, a means '203 receiving the multiple phase clock pulses and a retiming clock pulse selection signal so as to synthesize the retiming clock pulses in a way that the transition of the re-timing clock pulse takes place in the middle of the interval of the data bits received externally, and a means 204 applying re-timing to externally received data by using the synthesized re-timing clock pulse.</p> |
申请公布号 |
JPH09181713(A) |
申请公布日期 |
1997.07.11 |
申请号 |
JP19960316112 |
申请日期 |
1996.11.27 |
申请人 |
KANKOKU DENSHI TSUSHIN KENKYUSHO;KANKOKU DENKI TSUSHIN KOUSHIYA |
发明人 |
HIIYON JIYUN;BUMUCHIEORU RII;KUUONCHIYURU PAAKU |
分类号 |
H04L7/00;H04L7/02;H04L7/033;H04L7/04;(IPC1-7):H04L7/04 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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