| 摘要 |
<p>PROBLEM TO BE SOLVED: To make it possible to judge pulse widths in many channels in parallel, at high speed and at low costs by a method wherein, when the number of connected fundamental clock signals exceeds an upper-limit value or does not exceed a lower-limit value, an output is inverted so as to be held. SOLUTION: In an upper-limit judgment circuit at an upper-limit and lower- limit judgment circuit 5, when all BORROW signals in an upper-limit-value counter circuit 3 are at L, they are judged to be N.G. at an OR1 output the inverse of L, at a NAND8 output the inverse of H and at an INV7 output L. That is to say, when the number of counted fundamental clock signals exceeds upper-limit values at a PC1 to a PC3, the signals are judged to be N.G., and a CLER1 holds a result until a reset signal is input. On the other hand, in a lower-limit-value judgment circuit, when even one BORROW signal in a lower-limit-value counter circuit 4 is at H, outputs of FF's (NAND13, NAND14) are inverted at an OR2 output the inverse of H, at a NAND10 output the inverse of H and at a NAND output L, and, when the signal is at L, it is judged to be N.G. at an INV8 output. That is to say, when the number of fundamental clock signals does not exceeds a lower-limit value at a PC4 to a PC6, a CLER2 holds a result until the reset signal is input.</p> |
