发明名称 |
INPUT LINE INTERFACE DEVICE AND PACKET COMMUNICATION DEVICE |
摘要 |
<p>PROBLEM TO BE SOLVED: To reduce a post-stage processing load for performing routing control by efficiently housing the packets of a high speed line. SOLUTION: A packet assigning means 11 divides variable length packets, and assigns and outputs those variable length packets to parallel lines. Flow group classifying means 12-1 to 12-n classify the packets into flow groups for each of the parallel lines. A sequence number applying means 13 applies sequence numbers to the packets corresponding to the flow groups or independently. Buffering means 14-1 to 14-n perform the buffer storage and reading of the packets applied with the sequence numbers, and controls the arrangement of the packets in the flow groups. A flow assignment switch 15 assigns and outputs the packets to each flow group.</p> |
申请公布号 |
JP2002261826(A) |
申请公布日期 |
2002.09.13 |
申请号 |
JP20010060617 |
申请日期 |
2001.03.05 |
申请人 |
FUJITSU LTD |
发明人 |
KAWARAI KENICHI;NAGATA MASAKATSU;TOMONAGA HIROSHI;MATSUOKA NAOKI;KATO TSUGIO |
分类号 |
H04L12/951;H04L12/46;H04L12/773;H04L12/775;H04L12/953;H04L29/00;(IPC1-7):H04L12/56 |
主分类号 |
H04L12/951 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|