| 摘要 |
PROBLEM TO BE SOLVED: To improve the operation speed of a complementary pass transistor logic circuit (CPL). SOLUTION: The CPL is provided with input nodes I1-I4 provided with a first complementary input signal; intermediate nodes M1, M2 outputting complementary intermediated signals m, /m; a logic circuit network 10 consisting of an NMOS connected between the input nodes I1-I4 and the intermediate nodes M1, M2, controlled in conduction state by a complementary second signal (e.g. b, /b), and outputting a result of logical operation of the first input signal and the second input signal to the intermediate nodes M1, M2; and inverters 5, 6 for inverting the intermediate signals m, /m to generate complementary output signals. In the CPL, the NMOS of the logic circuit network 10 consists of depression type NMOSs (DMOSs 11-14). COPYRIGHT: (C)2006,JPO&NCIPI
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