| 摘要 |
A method of forming a gate electrode ( 24 ') for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer ( 26 ), for example formed of silicon-rich nitride, is deposited over a polysilicon layer ( 24 ) from which the gate electrode ( 24 ') is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer ( 29 ) is then formed over the hardmask layer ( 26 ), and photoresist ( 30 ) is photolithographically patterned to define the pattern of the gate electrode ( 24 '), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist ( 30 ) to the BARC layer ( 29 ). The remaining elements of the BARC layer ( 29 ) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer ( 26 ) by an anisotropic etch of that layer, using the trimmed BARC elements ( 29 ) as a mask. The hardmask layer elements ( 26 ') then mask the etch of the underlying polysilicon layer ( 24 ), to define the gate electrodes ( 24 '), having gate widths that are narrower than the minimum dimension available through photolithography.
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