Display device

摘要

Provided is to secure a data-writing period to a source line and reduce the number of the IC chips used. N image data (e.g., three image data, RGB) are sequentially input to one input terminal. Three switches, three first memory elements, three transfer switches, three second memory elements, and three buffers are connected in parallel to the input terminal. The three switches are turned on respectively. RGB image data are held in the three respective first memory elements. In a selection period of a gate line of an (m−1)-th row, image data of an m-th row are written to the first memory elements. When the three transfer switches are turned on in a selection period of a gate line of an m-th row, the image data are transferred to and held in the second memory elements. Then, the image data are output to each source line through each buffer.

主权项

1. A display device comprising:
a first functional circuit comprising:
a first input terminal inputted with a signal including n image data (n is an integer greater than or equal to 3); andn first transistors electrically connected to the first input terminal in parallel; a second functional circuit comprising:
n first memory elements;n second transistors; andn second memory elements; and a third functional circuit, wherein the first functional circuit divides the signal inputted to the first input terminal into n image data, wherein each of the n first memory elements is electrically connected to a corresponding one of the n first transistors, wherein the n first memory elements are inputted with the n image data, wherein each of the n second transistors is electrically connected to a corresponding one of the n first memory elements, wherein the n second transistors transfer the n image data held in the n first memory elements to the n second memory elements at the same timing, wherein the third functional circuit outputs the n image data held in the n second memory elements to n source lines, wherein channel formation regions of the n second transistors comprise oxide semiconductor layers including indium, wherein a wiring is connected to gates of the n second transistors, and wherein on/off of the n second transistors are controlled by a signal input to the wiring.