发明名称 |
NOISELESS BIT LINE AND DUMMY LINE STRUCTURE |
摘要 |
The structure senses the memory cell by comparing the bit line connected to a memory cell array(10) and the reference line connected to a dummy cell(30) through a sense amplifier(60). The reference line has intermediate potential level of the bit line. The size of the MOSFET forming the dummy cell is same to the one of the MOSFET of the memory cell. The potential level of the reference line is controlled according to the number of MOSFET of the dummy cell. The dummy cell uses same earth line(Vss) of the memory(10) and reference cell arrays.
|
申请公布号 |
KR960003399(B1) |
申请公布日期 |
1996.03.09 |
申请号 |
KR19920026928 |
申请日期 |
1992.12.30 |
申请人 |
HYUNDAI ELECTRONICS IND. CO., LTD. |
发明人 |
HA, CHANG - WAN |
分类号 |
G11C16/06;(IPC1-7):G11C16/06 |
主分类号 |
G11C16/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|