| 摘要 |
PURPOSE: To perform acceleration and to reduce a basic cell number by achieving the functions of subtraction and multiplication by using logic for the arithmetic operation of an Euclidean distance to be obtained at the time of viterbi decoding. CONSTITUTION: For I and Q signals inputted through an FFI, the viterbi decoding and parity check calculation are performed in a branch metric calculation part C1BMC 1 for C1, a C1 decoder 2, an encoder 3, a BMC 4 for C2, a C2 decoder and a decision circuit 7 system and decoded signals and C1 re-coding are obtained. In the meantime, the I and Q signals are passed through delay circuits 11 and 12, the result of demapping them in a demapping part 6 is inputted to a correction bit number counting part 8 and compared with the result of the decision circuit and an error corrected bit number is calculated. In the CIBMC 4, a plane is divided into plural areas and the Euclidean distance of a level 1 is obtained based on respective distance calculation tables for the respective areas. For the calculation, one of the three kinds of calculation formulas is selected and the logic is obtained only by the calculation formula selection signals of two bits and the error signals of three bits without performing actual calculation. |
