发明名称 CELL WITH UPPER LAYER WIRING TERMINAL
摘要 PROBLEM TO BE SOLVED: To provide an input/output terminal structure of a cell which relaxes limit of driving ability due to electromigration at the output by avoiding electrostatic breakdown of a gate oxide film at the input. SOLUTION: An LSI is provided with a multilayer metallic wiring and consists of a fundamental gate and a large-scale functional gate. Electrostatic breakdown of a gate oxide film due to connection of a long metal wiring is prevented at the input terminal. Limit of driving ability due to electromigration is relaxed at the output terminal by raising the input/output terminal of a fundamental cell and a functional cell constituting an LSI up to an upper layer metal wiring of a thick film in a vertical direction, and connecting each input/output terminal by using mainly a metal wiring of an upper layer, so that a long signal line disposed over a wide range in a chip inside such as a signal line transfer clock and a long signal line connecting large-scale functional cells constituting an LSI can be driven with high driving ability.
申请公布号 JP2002016144(A) 申请公布日期 2002.01.18
申请号 JP20000195900 申请日期 2000.06.29
申请人 TOSHIBA CORP 发明人 MORIMOTO HISAYOSHI;YAMAGUCHI AKIRA
分类号 H01L21/3205;H01L21/82;H01L21/822;H01L21/8238;H01L23/52;H01L27/04;H01L27/092;(IPC1-7):H01L21/82;H01L21/320;H01L21/823 主分类号 H01L21/3205
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