Memory controller and method for interleaving DRAM and MRAM accesses

摘要

A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.

主权项

1. A memory system comprising:
a volatile memory that includes a volatile memory array, wherein during an activate operation to the volatile memory, the volatile memory is configured to read a page of volatile data from the volatile memory array and store the page of volatile data in data-store latches of the volatile memory; a non-volatile memory that includes a non-volatile memory array, wherein during an activate operation to the non-volatile memory, the non-volatile memory is configured to read a page of non-volatile data from the non-volatile memory array and store the page of non-volatile data in data-store latches of the non-volatile memory, wherein an activate latency of the non-volatile memory is longer than an activate latency of the volatile memory; a shared data bus coupled to the volatile memory and the non-volatile memory; a shared address bus coupled to volatile memory and the non-volatile memory; and a memory controller coupled to the shared data bus and the shared address bus, wherein the memory controller is configured to:
initiate activate operations in the volatile memory and the non-volatile memory, including sending an address for the activate operations from the memory controller over the shared address bus to both the volatile memory and the non-volatile memory; andinitiate read operations for the volatile memory and the non-volatile memory, wherein the memory controller is configured to receive data for the read operations for the volatile memory and the non-volatile memory over the shared data bus,wherein the memory controller includes:
a first register that stores the activate latency of the volatile memory;a second register that stores the activate latency of the non-volatile memory;a third register that stores a precharge latency for the volatile memory; anda fourth register that stores a precharge latency for the non-volatile memory.