发明名称 Semiconductor package manufacturing method having an integrated circuit
摘要 The procedure involves forming a large number of groups of connection zones (104) on a common support substrate (102) by a matrix technique. These correspond to each of the fixing zones of the integrated circuit chips. A chip (103) is fixed on to each zone, and each chip is electrically connected to the associated electrical connection zones (104). This allows the formation of a flat assembly (111) of connected chip - substrate units. The procedure includes a second stage of placing this assembly (111) in a mould (112) and injecting a coating material (106) into the mould. This allows formation of a parallelepiped block (117) in a single operation. In a final stage the parallelepiped box (117) is cut through its thickness in order to form a semiconductor casing structure.
申请公布号 EP0883171(A1) 申请公布日期 1998.12.09
申请号 EP19980401318 申请日期 1998.06.02
申请人 STMICROELECTRONICS S.A. 发明人 EXPOSITO, JUAN;HERARD, LAURENT;CIGADA, ANDREA
分类号 H01L21/56;H01L23/31 主分类号 H01L21/56
代理机构 代理人
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