发明名称 RECEIVER
摘要 PURPOSE:To omit an intermediate-frequency amplifying circuit by detecting input signals with high frequency directly. CONSTITUTION:Frequency oscillated from a variable frequency oscillator 3 is synchronized with the divided frequency from a standard frequency oscillator 8 by the 1st PLL circuit consisting of a divider 7, a phase comparator 5, a low- pass filter 4, and a programmable divider 6. An output of the divider 7 is applied to a phase comparator 10 constituting the 2nd PLL circuit through a divider 9. An output from the 2nd variable frequency oscillator 12 is mixed with an input signal by a mixer 15 and a signal with the frequency corresponding to the difference between the mixed signals is passed through a band-pass filter 16 and applied to one input terminal of a phase comparator 17, which compares said input signal with an output obtained by dividing the output oscillated from the standard frequency oscillator 8 to control the standard frequency oscillator 3 so that its output is completely synchronized with the input signal of phase comparator 17. Consequently, the output of the variable frequency oscillator 3 is completely synchronized with said input signal, which is efficiency detected by a detecting means 1.
申请公布号 JPS57190413(A) 申请公布日期 1982.11.24
申请号 JP19810075210 申请日期 1981.05.18
申请人 MATSUSHITA DENKI SANGYO KK 发明人 UENO HIDEMI;FUKUI KIYOTAKE
分类号 H03J7/28;H03L7/23 主分类号 H03J7/28
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