| 摘要 |
PURPOSE:To simplify and facilitate the design of a pattern and to reduce the size of a chip, by providing a reference-potential wiring function in a grid-line isolating island, thereby omitting the layout of the reference potential wiring in a chip. CONSTITUTION:First and second secondary-conductor layers 13 and 14, whose conductivity types are different from the conductivity of a first conductor layer 12, are formed in an isolating island comprising the first conductor layer 12, which is formed on a semiconductor substrate 10. A first electrode pad 16 for inputting and outputting signals and an inner element input terminal 17 are provided on the first secondary-conductor layer. The second secondary-conductor layer 14 and a second electrode 19 having a reference potential are connected through a conductive gridline isolating island 11 formed on the semiconductor substrate 10. Therefore, the grid-line isolating island 11 has a reference potential wiring function and operates as a current returning path of a surge current. Thus the layout of the electrode wiring is reduced, the area of a chip is reduced and a low cost can be implemented.
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